A New LFSR Reseeding based Test Compression Scheme by Virtual Reduction of Smax

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. If the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, then successive n scan cells are filled with the same data so that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage than the previous test compression schemes.